Construction of integrated circuits requires the creation of many layers of material on a substrate of a silicon wafer. The layers are created in numerous steps, creating or depositing material first on the wafer and then polishing the wafer until the layer is very flat, or planarized. Some layers are created by deposition or etching of a circuit, with an intended irregular topology. Some layers are created by allowing the underlying layer to oxidize or otherwise react with the atmosphere, without the possibility of control over the flatness of the resultant layer. Thus, many of the layers must be polished to flatten or "planarize" the surface until it is suitably flat for creation of the next layer. The process of layer deposition and planarization is repeated many times over to create a number of layers with electronic circuitry on many of the layers and interconnects between the layers to connect this circuitry. The end result can be an extremely complicated yet miniature device. The complexity of the circuits which can be created depends on several factors, one of which is the degree of flatness which can be created in the planarization process, and the reliability of the planarization. Planarization of the layers preferably results in surface variation over a large area (500-1000 square millimeters on the order of 1000 angstroms or less.
One method for achieving semiconductor wafer planarization or topography removal is the chemical mechanical polishing (CMP) process. Chemical mechanical polishing (CMP) is a process for very finely polishing surfaces under precisely controlled conditions. In applications such as polishing wafers and integrated circuits, the process is used to remove a few angstroms of material from an integrated circuit layer, removing a precise thickness from the surface and leaving a perfectly flat surface. To perform chemical mechanical polishing, a slurry comprising a suitable abrasive, a chemical agent which enhances the abrasion process, and water is pumped onto a set of polishing pads. The polishing pads are rotated over the surface requiring polishing (actually, in processing silicon wafers and integrated circuits, the polishing pads are rotated under the wafers, and the wafers are suspended over the polishing pads and rotated). The amount of polishing (the thickness removed and the flatness of the finished surface) is controlled by controlling the time spent polishing, the distribution of abrasives in the slurry, the amount of slurry pumped into the polishing pads, and the slurry composition (and other parameters). While it is therefore important to control each of these parameters in order to get a predictable and reliable result from the polishing process, it is also desired to provide a method for determine when the wafer surface has been planarized to the specified flatness. Determination of when the wafer has been polished to the specified flatness is referred to as "endpoint detection." In a crude method, the wafer can be removed from its polishing chamber and measured for flatness. Wafers that meet the desired flatness specification can be passed onto further processing steps; wafers that have not yet been polished enough to meet the desired flatness specification can be returned to the polishing chamber, and wafers that have been over polished can be discarded. More advanced methods measure the wafer surface during the polishing process within the chamber, and are generally referred to as "in-situ" endpoint detection. Devices and methods for measuring wafer flatness by interpreting various wafer properties, such as reflection of ultrasonic sound waves, changes in mechanical resistance of the wafer to polishing, electrical impedance of the wafer surface, or wafer surface temperature, have been employed to determine whether the wafer is flat.
Recently, a process referred to as optical endpoint detection has been developed to measure the thickness of the top layer of a wafer. Optical endpoint detection refers to the process of transmitting a laser beam onto the surface of the wafer and analyzing the reflection. Most of the laser beam is reflected by the upper surface of the top layer of the wafer, by some of the laser beam penetrates the top layer and is reflected by the underlying layer. The two reflected light beams are reflected to an interferometer, which measures the interference between the two light beams. The degree of interference is indicative of the thickness of the layer, permitting precise determination of the layer thickness at the point of measurement. Numerous measurements over the surface of the wafer can be compared to obtain an overall indication of surface flatness. The process has been described in reference to plasma etching in Corliss, Semiconductor Wafer Processing With Across-Wafer Critical Dimension Monitoring Using Optical Endpoint Detection, U.S. Pat. No. 5,427,878 (Jun. 27, 1995), and in reference to chemical mechanical polishing in Birang, et al., Forming A Transparent Window In A Polishing Pad For A Chemical Mechanical Polishing Apparatus, U.S. Pat. No. 5,893,796 (Apr. 13, 1999). Birang describes a method of performing endpoint monitoring by passing a laser beam through a hole in the polishing pad and supporting platen. This hole is positioned such that it has a view of the wafer held by a polishing head during a portion of the platen's rotation in which the hole passes over a stationary laser interferometer within the CMP process chamber. The hole in the pad is filled with a transparent plug which is glued into the polishing pad. In this system, condensation and slurry seepage into the space under the window can interfere with the laser beam transmission, and imperfect match between the level of the pad and the level of the transparent plug can cause trenching in the wafer.